An energy-efficient image filtering interpolation algorithm using domain-specific dynamic reconfigurable array processor

With the development of micro-LED displays, the bicubic interpolation algorithm has become a critical technology. It is widely utilized in micro-LED displays to enhance the scaled details of video frames. However, the produced image exhibits the blurring effect and boundary artifacts after scaling. To address the above problems, we propose an image filtering interpolation algorithm. The smooth and Laplace filters are pre -filters to enhance image edges and reduce noise. The four corner-aligned bicubic interpolation algorithm has the highquality effect of scaling. Secondly, to enhance the processing speed and energy-efficient of the image filtering interpolation algorithm, a domain-specific dynamic reconfigurable array processor is also proposed, which contains a 8 x 8 processing element array with two types of heterogeneous processing elements. The processor supports the energy-efficient acceleration of the image filtering interpolation algorithm. To reduce hardware costs, we integrate the attributes of the smooth filter and the Laplace filter into a simplified composite filter. Besides, we utilize the efficient alternating line caching technology to eliminate the power consumption of repeatedly reading data through reorchestrates data cache order and keep reused data. The experiment results show that the peak signal-to-noise ratio of the proposed image filtering interpolation algorithm is 0.32 dB better than the state -of -the -art methods. In the implementation of the HLMC 55 nm process, the energy-efficient of the proposed processor is 23,661 MPixels/J. Moreover, the processing rate achieves 583.5 MPixels/s for three DRAP, enough to 3840 x 2160@60fps. Using alternating line caching technology, the reconfigurable array processor reduces 37.5% of line buffer resources.