A 28nm 8Kb Reconfigurable SRAM Computing-In-Memory Macro With Input-Sparsity Optimized DTC for Multi-mode MAC Operations

Computing-in-memory (CIM) is an emerging approach for alleviating von Neumann bottleneck and improving energy efficiency and throughput. This brief presents a reconfigurable SRAM CIM macro supporting multi-mode multiply-and-accumulate (MAC) operations, including binary weight network (BWN) MAC, ternary weight network (TWN) MAC, and multi-bit MAC operations. The BWN and the TWN topology are proposed for signed 5b-input MAC operation. The multi-bit MAC operation is achieved by both positive and inverse code with AND operation, which improves hardware utilization and doubles the throughput. To overcome the different dynamic ranges caused by reconfigurations, we proposed two adaptive solutions for different discharging capacitors, and an input-sparsity digital-to-time converter with intrinsic delay elimination to improve energy efficiency and linearity. The proposed 8Kb macro is fulfilled in a 28 nm CMOS with an energy efficiency of 1773.5 TOPS/W in BWN mode. The test chip achieves an accuracy of 84.35% on the CIFAR-10 dataset at 4b precision in inputs and weights.