Design and verification of a 10-bit asynchronous logic SAR ADC

In this paper, a simple, low-power, high-accuracy successive approximation analog-to-digital converter (SAR ADC) is designed. SAR ADC has a simple structure and obvious digital characteristics, and it generally does not need linear gain block units and other characteristics, so it can be well adapted to the evolution route of modern integrated circuit processes. With the rapid development of the CMOS integrated circuit industry, SAR ADC gradually becomes a research hotspot of analog-to-digital converters in recent years. The SAR ADC designed in this article achieves low power consumption by selecting a relatively low operating voltage and using a VCM-based capacitor array structure to form a differential capacitor array, a comparator block, and a successive approximation logic block. Based on the tsmc 65nm process, this paper realizes a SAR ADC with a supply voltage of 1.2V, a sampling frequency of 10Ms/s, an effective number of bits of 10.7121bit, and an SNR of 66.2471dB that meets the expected design requirements.