SLAC Serial Protocol (SSP) for 1 Gbps ASIC-to-FPGA Communication

The SLAC detector R&D program develops many X-ray detectors using a platform-based design where many Application Specific Integrated Circuits (ASIC) communicating with a single Field Programmable Gate Array (FPGA) are integrated into a detector system. These systems require a standard protocol to structure many data streams. This paper presents the SLAC Serial Protocol that provides a lightweight and customizable data stream up to 1 Gbps per lane. In order to demonstrate the protocol, 8B10B implementation results will be presented based on measurements from the ePix High Rate Monolithic X-Ray detector, which includes 24 LVDS data streams per ASIC.