A 28.9–38.8 μW dual-mode 10-bit column parallel single-slope ADC with minimum voltage feedback for CMOS image sensors

A dual-mode low-power column parallel single-slope (SS) ADC incorporating Minimum Voltage Feedback (MVF) is proposed for CMOS image sensors. When it works in low-power mode, the ADC utilizes a minimum voltage feedback approach and a dynamic bias structure to minimize the power consumption after the ramp signal surpasses the minimum voltage of a row. In its acceleration mode, it uses the minimum voltages extracted by the MVF circuit to improve the conversion speed. A 10-bit SS ADC with MVF was designed in a 0.18 μm CMOS process. The simulations have been performed to validate the proposed idea. The simulation results show that DNL and INL of the ADC are +0.124/-0.126 LSB and +0.15/-0.12 LSB, respectively. Moreover, the SNDR achieves 61.4 dB, the SFDR is 72.04 dB and the ENOB is 9.9 bit. Under the clock frequency of 100 MHz and the power supply of 3.3 V/1.8 V in the low-power mode, the simulated power consumption of the ADC ranges between 28.9 and 38.8 μW/column, with the column parallel comparator and ramp generator contributing to power reductions of up to 33.0 % and 53.5 %, respectively. The conversion time experiences a notable decrease of up to 65.4 % in the acceleration mode. The power consumption of the added MVF circuit is only 0.15 μW/column.