Synergistic Integration: An Optimal Combination of On-Die and Rank-Level ECC for Enhanced Reliability

Memory reliability is especially key to attaining resilience at scale, where effective error detection and correction are essential for ensuring data integrity and preventing system failures. Technologies such as On-Die Error Correction Code (OD-ECC) and Rank-Level ECC (RL-ECC) have evolved independently, mitigating various errors and enhancing reliability. However, investigating an optimal combination between OD-ECC and RL-ECC could lead to further improvements. In particular, the optimal scheme and mapping between OD-ECC with Bounded Fault (BF) applied and RL-ECC in DDR5 have yet to be explored. This paper investigates the importance of scheme consistency for reliability in memory sub-systems and provides guidelines for RL-ECC design for system companies.