Device-Architecture Co-optimization for RRAM-based In-memory Computing.

In the pursuit of high energy-efficiency computing solutions, RRAM-based in-memory computing (IMC) technology has emerged as a promising contender, offering notable advantages such as exceptional memory density, computing parallelism, and energy-efficiency. In this paper, we present a review of our optimization endeavors in RRAM-based IMC systems, spanning from the intricate device-level considerations to the overarching architectural aspects, highlighting the challenges and opportunities of this technology.