Concurrent Multiband CMOS Low Noise Amplifier Design for Internet of Things Applications.

This paper demonstrates a concurrent multiband Low Noise Amplifier (LNA) design with TSMC’s 40 nm CMOS technology for the internet of things application which has center frequencies at 2.45 and 5.6 GHz. The LNA employs a cascode common source with inductive degeneration circuit topology to obtain high gain, low noise figure, and low power consumption. The first concurrent dual-band LNA achieves input reflection coefficients (S 11 ) of -18.83 and -22.00 dB, forward gain (S 21 ) of 19.67 and 16.89 dB, and noise figure (NF) of 3.11 and 3.29 dB at 2.45 and 5.6 GHz, respectively. Furthermore, the LNA attains linearity of input 1-dB compression point (IP 1-dB ) of -21.3 and -18.18 dBm, and the third input interception point (IIP3) of -6.80 and -4.43 dBm at 2.45 and 5.6 GHz, respectively. The power consumption is 4.51 mW at 1.1V power supply. Additionally, the gain (S 21 ) can be enhanced to 20.08 and 21.97 dB at 2.45 and 5.6 GHz, respectively, with the proposed gate inductive peaking technique in the second design. This technique doesn't require additional power consumption. Both LNAs consume the same chip area of 0.48 mm ² .