Protecting SiC JFET from Gate Overstress in GaN/SiC Cascode Device without Compromising Switching Performance

The GaN/SiC cascode device featuring a low-voltage (LV) enhancement-mode (E-mode) GaN HEMT and a highvoltage (HV) SiC JFET has the unique capability of delivering thermally stable threshold voltage, avalanche capability, zero reverse recovery charge (Q _rr ), and fast switching speed simultaneously. However, the lack of avalanche capability in the LV GaN HEMT presents a challenging issue, namely the negative gate overstress of the HV SiC JFET during the switching process, which raises reliability concerns. A clamping unit based on a Si Zener diode can provide gate protection for JFET but inevitably increases the switching loss significantly due to the reverserecovery process of the Si Zener diode. This paper presents a new gate protection design based on a Si bi-directional Zener diode that can clamp the gate voltage of JFET without introducing the reverse-recovery process. Therefore, the gate of JFET can be protected while the switching performance of the cascode device is not compromised, as verified by the experiment results