Hybrid-FE-layer FeFET with High Linearity and Endurance Towards On-chip CIM by Array Demonstration

Analog weight cells based on ferroelectric field-effect transistors (FeFETs) are promising for fast and energy efficient compute-in-memory (CIM) accelerators, yet their on-chip training is hindered by the limited linearity and endurance. To address this critical issue, we introduced a novel FeFET design featuring a hybrid ferroelectric layer of Hf _0.5 Zr _0.5 O ₂ and Hf _0.95 Al _0.05 O ₂ with Al ₂ O ₃ interlayers. The proposed FeFET achieves a high linearity of α _p = -0.48 and α _d = -1.73, good endurance of over 10 ⁹ cycles, and a fast switching speed of ~50ns. The mechanism of such improvement was probed carefully by comparison with control devices. The benefit of device optimization was experimentally demonstrated by performing an on-chip training task on a 1T NOR array, and the system-level benchmarking of the CIM accelerator based on our FeFET shows an overall superior performance. This work contributes to the development of FeFETs for on-chip neuromorphic hardware.