An Automated Calibration Scheme for PLL in Time-to-Digital Converters

In high performance Time-to-Digital Converters (TDCs), PLL can be adopted to generate the required reference clock, which is in $\sim 100 \ \text{MHz}$ range. In order to improve the phase noise performance, the full VCO frequency range in such a PLL is generally divided into multiple sectors, which can be selected by digital code. This paper proposes an automated calibration scheme to set the digital code for optimized VCO performance. Primarily based on successive approximation algorithm, the proposed scheme completes the automated calibration with only minimal steps. By co-simulating with a typical PLL, the efficacy of the proposed scheme is fully validated. Tentatively synthesized using CMOS 180nm technology, the automated calibration scheme only occupies $100\times 100\text{um}^{2}$ of silicon area, and consists of 144 logical gates. The power consumption is only $\sim 100\ \text{uW}$ .