Overhead Optimized and Quadruple-Node-Upset Self-Recoverable Latch Design Based on Looped C-Element Matrix

In deep nanoscale and highly integrated complementary metal-oxide-semiconductor (CMOS) technologies, storage circuits are increasingly sensitive to multiple-node upsets (MNUs) caused by charge sharing. In order to mitigate the impact of MNUs, many MNU-hardened latches based on C-elements matrices have been proposed by research scholars. In this article, we analyze and summarize the MNU-hardened latches based on the C-elements matrix, and propose the connection rules and general fault-tolerance principle of the looped C-element matrix. Based on this design idea, we propose a low-overhead and highly reliable quadruple-node upsets (QNUs) self-recovery latch (referred to as QR-R11C2). The proposed latch is based on a looped C-element matrix with 11 rows and 2 columns, forming a heterogeneous interconnect scheme, which can provide complete self-recovery from QNUs in harsh radiation environments. Simulation results show that the proposed latch has the lowest power consumption, area-power-delay product, and setup time among existing QNU self-recovery latches. In addition, this article also analyzes and summarizes the MNU statistics of the looped C-element matrix-based latch designs and proposes an MNU self-recoverability verification method for looped C-element matrix-based latch designs. Taking the example of verifying the self-recoverability of six looped C-element matrix-based latches, the proposed verification method can reduce MNU combinations by 95.24%-99.99% compared to the exhaustive combinations.