High-Speed, Low-Power, and Area-Efficient 5T4M Memristor-Based Ternary Content Addressable Memory

Researchers are currently emphasizing the development of memory design based on memristors as a solution to the challenges posed by MOSFET-based designs. In this paper, a memristor-based ternary content addressable memory (MTCAM) has been designed and analyzed that is both high-speed and energy-efficient, while also occupying minimal area. The proposed MTCAM cell has five transistors and four memristors (referred to as 5T4M). It comprises two operational units: the main unit responsible for WRITE and SEARCH functions, composed of three transistors and two memristors, and the data recall unit, which is activated when data restoration is needed. This research work has been simulated in HSPICE with a 32-word array, each containing 144-digit MTCAM cells, using PTM 32 nm 0.9 V strained Si technology. The results indicate a search time of 204.6 ps and a search energy of 0.521 fJ/digit/search for worst-case mismatches, all achieved with a 1.2 V supply voltage. Furthermore, the implemented 32 x 144 MTCAM array provides a voltage margin of 331.38 mV. The 5T4M MTCAM design occupies an estimated area of 1.4904 mu m2, which is notably compact compared to existing designs.