HLS Based Design and Optimization of Merge Sort Algorithm for High Performance Computing

High level synthesis has emerged as a powerful tool for designing hardware algorithms for high performance computing systems. In this paper, we present an HLS based design and optimization of the merge sort algorithm for HPC applications. We use Xilinx’s Vivado HLS tool to generate hardware description language code from C based descriptions of the algorithm, and then optimize the code for throughput and latency using HLS directives. Our results demonstrate that the optimized merge sort algorithm provides a significant improvement in performance over traditional software-based implementations. Our work contributes to the growing body of research on using HLS for HPC applications. The proposed HLS based design and optimized merge sort algorithm shows the results like area usage, latency, efficiency, throughput in comparison with unoptimized merge sort.