Superior electrostatic control in uniform monolayer MoS2 scaled transistors via in-situ surface smoothening

Transistors with $2\mathrm{D}$ materials hold the promise for extreme gate length scaling enabled by the very thin channel, hence ultimate electrostatic control. However, to date, little has been demonstrated as channel defectivity impacts SS and variability. Here we report the demonstration of short channel transistors with $\mathrm{I}_{\text{OFf}}\leq 10\text{pA}/\mu \mathrm{m}$ for ultra-scaled devices, $\mathrm{I}_{\text{ON}}/\mathrm{I}_{\text{OFF}} >10^{7}$ , low median $\text{SS}_{\min}$ of 68mV/dec, and low VT variation with Pelgrom slope ( $\mathrm{A}_{\text{VT}}$ , a variability index) of $2.2\text{mV}-\mu \mathrm{m}$ . This is similar to sub-10nm fin width $(\mathrm{W}_{\text{fin}})$ Si FinFETs $(\text{EOT} =0.8\text{nm})$ with $\mathrm{A}_{\text{VT}}=2.5\text{mV}-\mu \mathrm{m}$ . The statistical analysis has been performed on more than 15000 devices, with smooth monolayer Mos2 deposited via MOCVD and an in-situ surface smoothening method, which precisely controls monolayer thickness and uniformity.