An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single-Stage Time-Based Gated-Ring-Oscillator ADC with $2\times$ Interpolating Sense-Amplifier-Latches

Circuit innovations in medium-low resolution ADCs are among the key enablers to achieving higher data rates, currently at 224Gb/s [1], in the next-generation data-communication links based on sophisticated DSP techniques. The ADC interleaving factor is defined by the spectral efficiency of the signaling format and the maximum DSP clock rate. At every new generation, the DSP size shrinks thanks to CMOS scaling. However, DSP clock rates are not increasing with new technology nodes. In the 5nm CMOS technology used, the power performance area (PPA) sweet spot for the DSP resides within 0.7-0.8V supply and 1-2GHz clock frequency range. Circuit innovations are necessary for the ADC to benefit from scaling as much as the DSP. The sub-ADC architecture should be highly digital, amenable to automatic layout synthesis and operate in the same sweet spot. In addition, with the sub-ADC clock rate and supply matching the DSP, latency is reduced, and level shifting is avoided. For the modern modulation formats 7-8b resolution is adequate. Time-based ADCs are promising architectures thanks to their highly digital implementation, replacing analog building blocks with digital counterparts.