Analyzing the Capacitance Coupling of Electrodes with a Solder Layer on the Transistor Footprint

This paper presented geometrical and calculation models of the TO-220, TO-263, SOT-89, and SOT-23-3 packages for SMD transistors. Using the constructed models, the capacitance matrices with and without the solder layer on the transistor electrodes were calculated. Comparison of the calculation results using the method of moments and the finite element method showed that their difference is no more than 14.8%. It is shown that taking into account the solder layer leads to an insignificant (no more than 20%) increase in the self-capacitance of the transistor electrodes. However, the maximum increase of drain-source (base-emitter) capacitance is 106.3% (SOT-89), and the minimum increase is 52.7% (SOT-23-3). The calculation results were used to create improved SPICE models of transistors, taking into account the package, footprint and solder. The models can be used in simulating various radioelectronic equipment, as well as in analyzing components for immunity to electrostatic discharge and electromagnetic interference exposure.