Improving FinFET Junctions and Contacts via Laser Annealing
2023 21st International Workshop on Junction Technology (IWJT)(2023)
摘要
Semiconductor industry transitions from the era of planar FETs to the era of three-dimensional (3D) transistors greatly improving performance per footprint. In planar FETs, the gate width W
G
, the lateral source/drain (S/D) size, and the metallic contact width W
C
are all equal to the transistor width W. FinFETs feature a 3D channel geometry where the gate perimeter W
G
per fin or, equivalently, the effective channel width W
eff
is significantly larger than the fin pitch P that defines the S/D and metallic contact width per fin (Fig. 1). Large W
eff
reduces the channel resistance but small P increases the parasitic external resistance R
EXT
making it a performance limiting factor. Innovative processes and new materials are required for reducing components of R
EXT
thereby realizing FinFET performance advantage. This work explores millisecond and nanosecond laser annealing techniques for reducing FinFET R
EXT
focusing on source/drain and contact resistances. Transistor-level specific contact resistivity in sub 10
-9
Ω-cm
2
range has been achieved for both nFETs and pFETs with corresponding improvements in R
EXT
and switching currents.
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关键词
3D channel geometry,channel resistance,contact resistances,effective channel width,fin pitch,FinFET junctions,gate perimeter,gate width,laser annealing,metallic contact width,nanosecond laser,parasitic external resistance,performance limiting factor,planar FET,semiconductor industry transitions,three-dimensional transistors,transistor width,transistor-level specific contact resistivity
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