The ESD Behavior of D-Mode GaN MIS-HEMT

This work investigates the electrostatic discharge (ESD) reliability and corresponding failure/ degradation mechanism of ${D}$ -mode GaN metal-insulator-semiconductor (MIS)-high electron mobility transistor (HEMT). Through the transmission line pulse (TLP) test and human body model (HBM) test, it is demonstrated that the gate structure of GaN MIS-HEMT exhibits an asymmetric behavior in the forward and reverse ESD stress, which can attribute to the asymmetric forward and reverse gate capacitance. With the forward ESD pulses applied, the devices’ gate shows a high ESD robustness (TLP failure current higher than 6 A), which can be contributed to the high forward gate capacitance. Because the gate capacitance under the reverse voltage is very small, there is almost no TLP current with the reverse TLP pulses applied to gate electrode. It is also found that, the device exhibits greater ESD robust in the D-to-G situation (2600 V in HBM test) than that in the S-to-G situation (1000 V in HBM test), which results from the longer G-to-D distance. Although the device gate structure can withstand a very high ESD voltage, it may already undergo severe degradation when subjected to a smaller ESD voltage. Therefore, it is necessary to integrate a bi-directional ESD protection device between the device’s gate and source electrodes during the circuit design. In addition, for the S-to-D and D-to-S situation, the devices have not failed even with the applied pulse voltage increased to 1000 V in TLP test and 8000 V in HBM test.