Crosstalk Mitigated On-chip Interconnect Design for High-speed Network-on-Chip (NoC) of Full Wafer Scale Chip (FWSC)

Full wafer scale chip (FWSC) is a promising AI computing architecture that integrates the entire wafer into a single chip, surpassing the limitations of off-chip interconnect. The large-scale FWSC requires communication between cores separated by long and dense on-chip interconnect which can induce SI problems like crosstalk. In this paper, we designed and analyzed the on-chip interconnect of the 2D mesh Network-on-Chip (NoC) for the FWSC. We introduced a power/ground shield for the on-chip interconnect, significantly reducing the crosstalk effect. Additionally, we added a feed-forward equalizer (FFE) to the transceiver (Tx) to compensate for inter-symbol interference (ISI) due to the shield. On-chip interconnect with 5 nm process technology was designed and analyzed using full 3D electromagnetic (EM) and circuit simulations. As a result, the proposed design effectively mitigated crosstalk effects and improved the timing jitter by 79.4%.