A 12~14.6GHz Fractional-N Sub-Sampling PLL for Wavelength Modulation Spectroscopy of CSMCs

This paper presents a fractional-N sub-sampling PLL (SSPLL) for wavelength modulation spectroscopy of chip-scale molecular clocks (CSMCs). The proposed SSPLL adopts a 5-bit vector modulator (VM) based phase-interpolator (PI) and a 5-bit digital-to-time converter (DTC) for in-band phase noise suppression. The proposed 5-bit VM based PI achieves high phase linearity with INL/DNL < 0.25 LSB. It reduces the required dynamic range and intrinsic jitter of the DTC. According to the simulation, the SSPLL spans from 12GHz to 14.6GHz with a rms jitter of 99.4fs, The DC power consumption is 26.7mW. The SSPLL’s figure-of-the-merit (FoM) achieves -245.8 dB.