A 22nm 56TOPS/W 6/8-bit Linearly-scalable R-2R Multiply-and-Accumulate Architecture with 2.2ns Latency.

This paper presents a current-domain compute-in-memory (CIM) architecture for acceleration of Artfficial Intelligence (AI) edge inferencing. A novel multiply-and-accumulate (MAC) scheme is introduced by exploiting the R-2R resistor ladder as a binary-weighted current recombiner. The area and power of the proposed scheme scale linearly as numerical precision increases for both input activation and weight. Computation latency is maintained single cycle. A prototype in 22nm FDSOI CMOS process achieves 2. 2ns system latency, 56TOPS/W energy efficiency and 4TOPS/m$\mathrm{m}^{2}$ area efficiency with 6-bit input activation and 8-bit weight.