C-V measurement and modeling of double-BOX Trap-Rich SOI substrate

In this paper, we propose a new Double-BOX structure for the characterization of the electrical properties of the trap-rich layer used to improve the radio frequency performance of Silicon-on-Insulator substrates. Capacitance voltage (C-V) measurement is used in this investigation. The experiment reveals anomalous C-V behaviors with a plateau appearing in the electron accumulation region and a shift towards negative voltages in hysteresis. According to the TCAD simulation, it is found that both of them are caused by the deep trap states in the polysilicon near the front interface. Based on the C-V hysteresis, the density of the deep trap states can be determined from measurements.