Radiation Tolerant Reconfigurable Hardware Architecture Design Methodology

The purpose of this research topic is to investigate the properties of reconfigurable devices (i.e., FPGA) under a radiation environment to finally propose a new methodology to design and evaluate cost-effective radiation hardening measures for reconfigurable devices. As a first step, the radiation hardness of an existing common off-the-shelf reconfigurable hardware device (FPGA) is investigated with regard to different radiation sources, including fast neutron radiation and gamma radiation. Therefore, an experiment is proposed to evaluate in run-time the changes on the memory configuration logic (e.g., configuration of each LUT, routing switches, connection boxes, DSPs,...) and memory user logic (e.g., content of each Block RAM, Flip-Flop, Distributed RAM implemented on LUTs,...). As a result, the chosen FPGA will be modelled in terms of fault probability of each FPGA component for a given radiation environment. These models will be integrated in a new simulation fault injection environment. In a third step, new cost-effective radiation hardening mechanisms, including configuration adjustments, design redundancy, and specialized hardware designs with error detection and correction, will be proposed and evaluated using the previously proposed environment. The proposed radiation hardening mechanisms shall be verified by using real-world radiation sources. The goal is to provide a new methodology for the design of radiation tolerant hardware architecture for FPGA devices.