A 0.0033 mm(2) 3.5 fJ/conversion-step SAR ADC with 2x Input Range Boosting

This paper proposes an input range boosting technique for successive-approximation-register (SAR) analog-todigital converters (ADC). By performing a pre-comparison and switching the DAC accordingly, the input range of a SAR ADC can be doubled with limited power and area overhead. This effectively improves the power efficiency by relaxing the noise requirement and improves the area efficiency by using less DAC capacitors. A prototype ADC is fabricated in 65 nm CMOS and occupies an area of 0.0033 mm(2). It consumes 34.06 mu W at 10 MHz sampling rate from a 1 V supply. The measured SNDR is 62 dB for a 5 MHz bandwidth, resulting in a Walden figure of merit (FoM(W)) of 3.28 fJ/conversion step.