A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications.

This paper presents a dual-edge-triggered flip-flop (DET-FF) with redundant internal node transition elimination (RTEDET) to achieve minimal dynamic power consumption. The proposed RTEDET shows lower total power by 37%/39% than the recent low-power flip-flop/conventional DET-FF thanks to the halved CK frequency and the redundant internal node transition elimination. In addition, the proposed RTEDET can operate at supply voltage down to 0.35V in all chips with its static operation and contention-free feature.