A Hypergraph Model and Associated Optimization Strategies for Path Length-Driven Netlist Partitioning

Prototyping large circuits on multi-FPGA platforms requires to partition the circuits into sub-circuits, each to be mapped in a given single FPGA. While most existing partitioning algorithms focus on minimizing cut size, the main issue is not to map long paths across multiple FPGAs, as it may cause an increase in critical path length. To address this problem, we propose a new hypergraph model, for which we design algorithms for initial partitioning and partition refinement. We integrate these algorithm in a multilevel framework, combined with existing min-cut solvers, to tackle simultaneously both path length and cut size objectives. We observe a significant reduction in critical path degradation, by 12%–40%, at the cost of a moderate increase in cut size, compared to path-agnostic min-cut methods.