(Digital Presentation) Selective SiGe Vapor Etching Using Br₂ in View of Nanosheet Device Isolation

Forksheet transistors are lateral nanosheet devices with a forked gate structure [1,2]. The physical separation of N- and PFETs by a dielectric wall enables N-P space scaling and consequently sheet width maximization within the limited footprint of low-track-height standard cells. Bottom dielectric isolation has been proposed to circumvent the junction isolation trade-off between punch-through suppression on the one hand and junction leakage and capacitance on the other hand [3]. A typical fabrication scheme includes the epitaxial growth of Si/Si1-yGey/multi-{Si1-xGex/Si} epi stacks (y>x) where the bottom Si1-yGey layer is later replaced by a SiN/SiCO isolation [4]. The fabrication scheme relies on selective etching of the sacrificial Si1-yGey layer with respect to the {Si1-xGex/Si} multi-stack. Owing to the very small dimensions (e.g. sub-10 nm nanowire channel diameter), high etch selectivity towards both Si1-xGex and Si, and excellent process controls are mandatory. This sets stringent requirements on the epitaxial stacks (thicknesses and composition control, sharpness of interfaces, and absence of strain relaxation) [4] as well as on the etch process itself (high selectivity, limited Si1-xGex and Si consumption) [5-7]. The selective Si1-yGey removal requires a great precision in its adjustment, with the risk of experiencing process variabilities and yield issues. Selective SiGe etching is typically done in advanced wet or dry chemistries and is sensitive to both strain in and oxidation of individual layers [4-6]. Also, HCl-based vapor etching has been reported for SiGe removal, with high selectivity towards Si [7]. The HCl vapor etching requires a sufficiently high process temperature (typically ≥ 600°C). This makes it less attractive for fabrication schemes with bottom isolations. The presence of the Ge-rich Si1-yGey layer in the as-grown epi stack results in an enhanced risk for unwanted layer relaxation. A low temperature Br2-based vapor etching process is proposed as an alternative for the selective Si1-yGey removal in the isolation fabrication. After initial process screening on blanket epi layers to compare etching behavior for different process gases as function of material composition and crystallinity, it is demonstrated on patterned test structures that Br2 etching enables high etch selectivity of Si0.5Ge0.5 towards Si and Si1-xGex (x=0.2, 0.23, and 0.3). Figure 1 compares the etching characteristics of HCl, HBr, and Br2 as obtained for blanket Si1-xGex layers where the Ge content was varied between 0.2 and 0.5. In all cases, the etching is kinetically controlled. The etching rates indeed show a clear exponential dependence as function of the process temperature. While the etching rates are similar for HCl and HBr, the Arrhenius plot is shifted to ~300°C lower temperatures for Si1-xGex etching with Br2. For each process gas, the etching rate increases with increasing Ge concentration. This difference in etching rate as function of layer composition is highest for Br2. Figure 2 reports the obtained etching selectivity between Si0.5Ge0.5 and Si1-xGex (x = 0.15 – 0.36) as obtained for Br2 etching on blanket wafers. Selective etch tests with Br2 as etching gas were conducted on fin patterned structures consisting of Si-substrate / 10 nm Si0.5Ge0.5 / 3x {9 nm Si1-xGex / 9 nm Si}. Different etching times have been applied to demonstrate the concept and to validate etch selectivity between Si0.5Ge0.5 and Si1-xGex/Si. Figure 3 displays low magnification X-TEM images of the structure with x=0.2, after fin patterning, 1 min, and 3 min Br2 etching. The selective etching of the Si0.5Ge0.5 layer is clearly demonstrated, although the shortest etching time is not sufficient for complete Si0.5Ge0.5 removal while the sample etched for 3 min was clearly over etched. Lateral material loss of the upper two Si0.8Ge0.2 layers is limited to 2-3 nm (Fig. 3b) and 3-4 nm (Fig. 3c), respectively. During lateral Si0.5Ge0.5 etching, the lowest Si0.8Ge0.2 layer gets exposed to the Br2 etching gas both from the side walls as well as from the bottom surface. The severe etching of this layer is also observed for other etching routines and can easily be avoided by adding a thin Si layer between the Si0.5Ge0.5 layer and the first Si0.8Ge0.2 layer. References: [1] P. Weckx et al., 2017 IEEE IEDM, 20.5.1. (2017) [2] H. Mertens et al., 2021 IEEE Symp. on VLSI Techn ., T 2.1 (2021) [3] J. Zhang et al., 2019 IEEE IEDM, 11.6.1. (2019) [4] A. Hikavyy et al., ECS Trans. 104 (4), p. 139 (2021) [5] Y. Muraki et al., Advanced Etch Technology and Process Integration for Nanopatterning XI, 12056-6 (2022) [6] Y. Oniki et al., Surface Preparation and Cleaning Conference (SPCC), (2020) [7] J. M. Hartmann et al., Semiconductor Science and Technology 25 (10), 105009 (2010) Figure 1