Radiation hard true single-phase-clock logic for high-speed circuits in 28 nm CMOS

Abstract True Single-Phase-Clock (TSPC) dynamic logic is widely used in high-speed circuits such as high-speed SERDES (Serializer/Deserializer) and frequency dividers. TSPC flip-flops (FF) are known for their high operational speed and low power consumption, compared to static FFs. Due to the relatively high leakage currents in modern CMOS processes, the use of leakage protection techniques of the storage nodes in TSPC must be considered, especially at high radiation doses. In this paper, the limitations originating from Total Ionization Dose (TID)-induced subthreshold leakage currents are analysed and radiation-hardening-by-design (RHBD) circuit techniques are proposed. Additionally, Single Event Upsets (SEU) are investigated by quantifying the critical charge of the leakage protected TSPC FF. The results are compared to both the static and the TSPC FF without leakage mitigation.