PEPA: Performance Enhancement of Embedded Processors through HWAccelerator Resource Sharing

To improve the performance while reducing the power consumption, embedded processors in Systems-on-Chip (SoC) often now include tightly coupled hardware accelerators that can execute dedicated tasks orders of magnitude more efficiently (faster and lower power). These hardware accelerators though require significant hardware resources as one of the main reason for their efficiency is that they extensively exploit the parallelism of these dedicated tasks mapped on them. The question that we address in this work is if these hardware resources can be re-used by the CPU when executing a different application. To address this, in this work we propose an integrated methodology that adapts automatically the CPU architecture with the tightly integrated hardware accelerator(s) such that any applications that will run on the CPU (different from the accelerator) can benefit from the additional hardware resources available in the hardware accelerator(s), such that the execution of these applications is accelerated. We also propose a VLIW compiler backend that based on the resources shared, re-generates the assembly instructions such that the new applications can benefit from this new architecture. Experimental results show that our proposed methodology is very effective, achieving average speed up of 1.7x.