Ferroelectric Engineering of FeFET Toward Multi-Level Coding for High-Density Nonvolatile Memory
2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT)(2023)
摘要
The prospect of ferroelectric oxide by ALD (Atomic Layer Deposition) with bistable nature feature of hysteresis loops satisfies the demands of the storage signal purpose for memory. An inserted Al
2
O
3
insulator to separate the ferroelectric layers and to avoid the formation of non-ferroelectric phases is a useful method to enhance the memory window (MW) for multi-level cell (MLC) applications. The nonidentical double-HfZrO
2
(HZO) FeFET has not only a larger MW than single HZO but also improve error rate (ER). Recently, superlattice (SL) HfO
2
-ZrO
2
with physical thickness of 5 nm and low phase fraction ratio 0.101:1 of monoclinic-phase (m-phase) to orthorhombic-phase (o-phase) investigated by geometrical phase analysis (GPA) is demonstrated. The homogeneous and congruous of SL-HfZrO
2
(HZO) with sufficient f erroelectric-domain is integrated as multi-HZO stack FeFETs for multibit NVM with low |V
PG/ER
| = 4 V, ultra-low error rate = 7.5×10-16, record high 2-bit endurance for 109 cycles, and stable data retention > 104 s. The superlattice technique for FE-HZO is a promising concept with elevating the coherence of domain access due to high o-phase toward emerging memory applications.
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