IPDeN 2.0: Real-time NoC with selective flit deflection and buffering

Network-on-Chips (NoCs) have proven to be a good alternative to traditional bus-based communication architectures to interconnect all programming elements (PEs) in modern Multiprocessor Systems- on-Chips (MPSoC). Wormhole switching with Virtual-Channels (VCs) and deflection-based routing policy are the most commonly used strategies to develop NoCs for real-time systems. Deflection-based solutions have shown to be the more suitable option for systems with power and/or area constraints. However, because flits may be deflected to alternative routes when traversing the network toward their destination, their traversal times may increase. In this paper, we propose IPDeN 2.0, a new NoC that combines the benefits of buffers with the concept of deflection to avoid flits from always being deflected in contention scenarios, thus ensuring shorter communication time of flits. The proposed design also guarantees in-order flit delivery at the destination. Contrary to VCs-based NoCs, the proposed solution does not rely on expensive buffering mechanisms. Instead a single small buffer is added to each router. The buffer size is fixed and depends only on the network topology. Experimental results show that flits see their actual traversal and communication times reduced in IPDeN 2.0 as compared to IPDeN and HopliteBuf NoCs (its closest competitors) without affecting the upper-bounds on worst-case traversal and communication times. We also implemented IPDeN 2.0 using the Verilog hardware description language. We synthesize our solution for a medium-sized FPGA platform. We show that IPDeN 2.0 requires approximate to 50% less hardware resources than NoCs that rely on VCs.