A 0.9-V 50-MS/s 67.3-dB-SNDR SAR-ISDM ADC With an Oscillator-Based Integrator

A two-step analog-to-digital converter (ADC), using a successive approximation register (SAR) ADC and a time-domain incremental $\Sigma \Delta $ modulator (ISDM) for the coarse and fine conversion, is proposed for power-efficient data conversion. A high-gain gated-delay oscillator (GDO) with a time-domain integration technique is employed to achieve the first-order noise shaping in the fine ISDM conversion. The proposed ADC fabricated in a 40-nm CMOS technology achieves a peak SNDR of 67.3 dB, the Schreier figure of merit (FoM $_{\text {S}}$ ) of 169.27 dB, and the Walden figure of merit (FoM $_{\text {W}}$ ) of 16.76 fJ/conversion-step.