Word2Vec FPGA Accelerator Based on Spatial and Temporal Parallelism

Word2vec is a word embedding method that converts words into vectors in such a way that the semantically and syntactically relevant words are close to each other in the vector space. Acceleration is required to reduce the processing time of Word2vec. We propose a power-efficient FPGA accelerator exploiting temporal and spatial parallelism. The proposed FPGA accelerator has the highest power-efficiency compared to existing top-end GPU accelerators. It is more power efficient and nearly two times faster compared to a previously proposed highly power-efficient FPGA accelerator.