A 16GHz 33fs rms Integrated Jitter FLL-less Gear Shifting Reference Sampling PLL

As the required data rate has gradually increased in recent years, the phase noise specification of the local oscillator (LO) in the RF standards becomes very stringent. For example, 5G new radio (NR) standards demand sub-100fs rms jitter at various channels [1]. A conventional charge-pump (CP) PLL is one of the candidates in low noise PLL design. However, to achieve the low in-band noise from the CP, the reset delay of phase-frequency-detector (PFD) should be small, which is difficult to implement since it has trade-off relationship with the dead zone problem of CP and PFD [2] [3]. A sub-sampling PLL (SSPLL) can achieve a very low in-band noise by sampling the voltage-controlled oscillator (VCO) edge directly and the divider noise can be eliminated [4]. However, this architecture has very narrow frequency capture range and its bandwidth suffers from process-voltage-temperature (PVT) variation. A reference sampling PLL (RSPLL) can also significantly reduce in-band noise by sampling behavior similar to SSPLL [1]. This structure has moderate capture range and its bandwidth is more insensitive to PVT variation than SSPLL. However both sampling PLLs have a small frequency capture range compared to CPPLLs, they need additional frequency tracking loop (e.g., a frequency-locked loop (FLL)) which leads to increase power and design complexity. In this paper, we propose a low noise RSPLL with a gear shifting (GS) scheme which supports a simple and robust PLL locking process. The proposed PLL is fabricated in a 5nm FinFET CMOS technology and dual frequency bands (16GHz and 10GHz) can be supported. The PLL achieves 33fs rms at 16GHz and 36.6fs rms at 10GHz.