State Access for RSFQ Test and Analysis

We present means to initialize, to propagate, and to examine states in an RSFQ circuit that are useful for design as well as for functional test and analysis. Our RSFQ test strategy distinguishes states by the information they carry from computation to computation, and saves costs by ignoring information-free states. To start, stop, and stall operations that are asynchronous, we developed a new variety of RSFQ stateholder, called MrGO after its CMOS counterpart. We include two simulated examples, a clocked pipelined adder for which we test functionality, and an asynchronous ring FIFO for which we analyze throughput.