Optimized Full Adder-Subtractor in QCA for nano-computing applications

At present, high speed and low power consuming circuits are required for computation at nano-scale levels to conquer the daily increasing demands of the human beings. Due to many limitations such as power dissipation, leakage current and breakdown of Dennard scaling, CMOS (Complementary Metal Oxide Semiconductor) technology era is now reached to its final stage. Quantum-Dot Cellular Automata (QCA) technology does not have these limitations and proved itself a perfect alternate of CMOS technology. This paper presents an area and cost optimized QCA Full adder-subtractor using QCA designer tool and also compared with the previous designs available in literature. The comparison of results have been done on the basis of performance parameters such as number of QCA cells, area, delay and cost function. It has been observed that the proposed layout achieved 28%, 33% improvement in number of cells and cost function respectively.