A Comprehensive Modeling Platform for Interconnect Technologies

With device scaling facing major physical and manufacturing challenges, many research efforts have been focused on the impact of device parameters and designs on circuit performance and power dissipation. However, similar research on the impact of Cu-low ${k}$ interconnects at the advanced nodes and the potential benefits offered by novel wire and via material and process options is lacking. While studies based on smaller circuit blocks exist, the exploration of these benefits for the performance of larger processors is lacking although the limits imposed by interconnect resistances become more severe due to longer wires and increased complexity in larger circuits. In this article, we conduct a study to quantify the effect of back-end-of-the-line (BEOL) technology improvements on circuit power, performance, and area (PPA) of various circuits from small blocks up to a full commercial processor with L1-cache. We modified the interconnect technology (ICT) files for the ASAP7 process design kit (PDK) to reflect various BEOL options such as thinner barrier/liners, near barrierless vias, and alternative material options based on TCAD simulations. We show that these options can offer up to a $1.769\times $ improvement in effective frequency or up to three metal-level savings.