Symmetric and Excellent Scaling Behavior in Ultrathin n- and p-Type Gate-All-Around InAs Nanowire Transistors

Complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) are the key component of a chip. Bulk indium arsenide (InAs) owns nearly 30 times higher electron mobility mu(e) than silicon but suffers from a much lower hole mobility mu(h) (mu(e)/mu(h) = 80), thus unsuited to CMOS application with a single material. Through the accurate ab initio quantum-transport simulations, the performance gap between the NMOS and PMOS is significantly narrowed is predicted and even vanished in the sub-2-nm-diameter gate-all-around (GAA) InAs nanowires (NW) FETs because the inversion of the light and heavy hole bands occurs when the diameter is shorter than 3 nm. It is further proposed several feasible strategies for further improving the performance symmetry in the GAA InAs NWFETs. Short-channel effects are effectively depressed in the symmetric n- and p-type GAA InAs NWFETs till the gate length is scaled down to 2 nm according to the standards of the International Technology Roadmap for Semiconductors. Therefore, the ultrasmall GAA InAs NWFETs possess tremendous prospects in CMOS integrated circuits.