Rule-Based Design for Low-Cost Double-Node Upset Tolerant Self-Recoverable D-Latch.

IEEE Access(2023)

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摘要
This paper presents a low-cost, self-recoverable, double-node upset tolerant latch aiming at nourishing the lack of these devices in the state of the art, especially featuring self-recoverability while maintaining a low-cost profile. Thus, this D-latch may be useful for high reliability and high-performance safety-critical applications as it can detect and recover faults happening during holding time in harsh radiation environments. The proposed D-latch design is based on a low-cost single event double-node upset tolerant latch and a rule-based double-node upset (DNU) tolerant latch which provides it with the self-recoverability against DNU, but paired with a low transistor count and high performance. Simulation waveforms support the achievements and demonstrate that this new D-latch is fully self-recoverable against double-node upset. In addition, the minimum improvement of the delay-power-area product of the proposed rule-based design for the low-cost DNU tolerant self-recoverable latch (RB-LDNUR) is 59%, compared with the latest DNU self-recoverable latch on the literature.
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关键词
Latches,Transistors,Inverters,Power demand,Delays,Impedance,Computer architecture,Delay-power-area product (DPAP),double node upsets (DNU),high impedance state (HIS),low cost single event double node upset tolerant (LSEDUT),power-delay product (PDP),single node upset (SNU),soft error (SE)
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