A Routing-Aware Mapping Method for Dataflow Architectures.

Dataflow architecture is a promising parallel computing platform with high performance, efficiency and flexibility. Dataflow mapping algorithm offloads programs onto dataflow hardware, which has a significant impact on the performance of the architecture. Dataflow mapping methods in previous studies are hardly efficient as they rarely consider the requirements of routing resources. In this paper, we propose a routing-aware mapping algorithm by combining hardware resources and dataflow graph characteristics to explore better mapping schemes. Our method first focuses on the influence of predecessor and successor nodes when mapping a node, and then comprehensively considers the competition of computing resources and the routing cost, to find the mapping solution with the lowest overhead. Experiments demonstrate that our method can achieve up to 2.06x performance improvement and 12.8% energy consumption reduction compared to state-of-the-art methods.