High-Performance Bilayer WSe2 pFET with Record Ids = 425 μA/μm and Gm = 100 at μS/μm Vds = -1 V By Direct Growth and Fabrication on SiO2 Substrate

In this work, we demonstrate high-performance bilayer $\mathrm{W}\mathrm{S}\mathrm{e}_{2}$ pFETs by direct CVD growth and fabrication on $\mathrm{S}\mathrm{i}\mathrm{O}_{2}$ substrate without a transfer process. The transistors exhibit low contact resistance of 0.65 $\mathrm{k}\Omega\cdot\mu \mathrm{m}$ which stays ohmic down to 4.3 K measurement temperature, indicating negligible Schottky barrier height between the Pt metal contact and bilayer $\mathrm{W}\mathrm{S}\mathrm{e}_{2}$. EOT scaling is systematically studied with $\mathrm{S}\mathrm{i}\mathrm{O}_{2}$ thickness from 100 nm down to 6 nm, and also on a 2 nm $\mathrm{S}\mathrm{i}\mathrm{O}_{2}/10$ nm HfLaO dielectric, showing clear improvement of short channel effects. The bilayer $\mathrm{W}\mathrm{S}\mathrm{e}_{2}$pFET o$\mathrm{f}\mathrm{L}_{\mathrm{c}\mathrm{h}}=120$ nm exhibits record $\mathrm{I}_{\mathrm{d}\mathrm{s}}=425\mu \mathrm{A}/\mu \mathrm{m}$ and $\mathrm{g}_{\mathrm{m}}=80\mu \mathrm{S}/\mu \mathrm{m}$ on the 6 nm $\mathrm{S}\mathrm{i}\mathrm{O}_{2}$, and $\mathrm{I}_{\mathrm{d}\mathrm{s}}=370\mu \mathrm{A}/\mu \mathrm{m}$ and $\mathrm{g}_{\mathrm{m}}=100\mu \mathrm{S}/\mu \mathrm{m}$ on the $\mathrm{S}\mathrm{i}\mathrm{O}_{2}/$HfLaO dielectric with a subthreshold slope of 200 $\mathrm{m}\mathrm{V}/\mathrm{d}\mathrm{e}\mathrm{c}$ and 250 $\mathrm{m}\mathrm{V}/\mathrm{d}\mathrm{e}\mathrm{c}$, respectively. This work exhibits significant progress of p-type 2D transistors in terms of material growth, fabrication, and device performance, providing new solutions for promoting the development of 2D CMOS devices.