A 1.1μs 1.56Gb/s/mm 2 Cost-Efficient Large-List SCL Polar Decoder Using Fully-Reusable LLR Buffers in 28nm CMOS Technology.Dongyun Kam,Byeong Yong Kong,Youngjoo LeeSymposium on VLSI Technology (VLSI Technology)（2022）引用 1|浏览2暂无评分AI 理解论文溯源树样例生成溯源树，研究论文发展脉络Chat Paper正在生成论文摘要
