Charged Defect Simulation in SiDB Systems

Experimental demonstration of nanometer-scale logic devices composed of atomically sized quantum dots, combined with the availability of SiQAD, a computer-aided design (CAD) tool designed for this technology, have sparked research interest in future atomic-scale logic systems based on these quantum dots. These studies range from gate designs all the way to new electronic design automation frameworks, resulting in synthesized circuits reaching the size of $32\times10^3\,$nm$^{2}$, which is orders of magnitude more complex than their hand-designed counterparts. However, current simulation capabilities offered by SiQAD do not include defect simulations, meaning that near-surface imperfections are not taken into account when designing these large SiDB layouts. This work introduces fixed-charge simulation into SimAnneal, the main SiDB charge configuration simulator of SiQAD, to cover an important class of defects that has a non-negligible effect on the behavior of nearby SiDB charge states at non-negligible distances -- up to 10 nm and beyond. We compared the simulation results with past experimental fittings and found the results to match fairly accurately. For the three types of defects tested, T1 arsenic, T2 silicon vacancy, and a stray SiDB, the root mean square percentage errors between experimental and simulated results are 3%, 17%, and 4% respectively. The availability of this new simulation capability will provide researchers with more tools to recreate experimental environments and perform sensitivity analyses on logic designs.