Using All-Digital On-chip Syntonistor to Compensate Clock Frequency Error in Network Time Synchronization for Accuracy Reaching to Sub-µs Range

The emergence of Internet of Everything has made time awareness a feature of high priority. One of the enabling factors is time synchronization. High-quality synchronization demands frequency source of high stability, which is pricey and bulky. When low-end source is used, synchronization quality would be severely impaired. This situation can be improved by the technique of time synchronization. In mainstream approaches, however, the frequency of clock pulse train is not tuned due to the lack of appropriate tool. As requirement for synchronization advances into microsecond or even nanosecond regime, frequency tuning in hardware is expected to be beneficial. Moreover, wireless networks do not have frequency transfer mechanism. This exacerbates the problem of frequency deviation. Those issues make syntonization (synchronization of frequency) become necessary. In this work, an all-digital frequency-tunable clock source is used as on-chip syntonistor to physically compensate the clock frequency errors of nodes in a network. Time discrepancies are hence alleviated. A wireless network has been built to validate this scheme. Time synchronization quality has reached to sub-µs range. The key contribution is the suggestion of adopting on-chip syntonistor for improving the quality of network synchronization. This work serves as a demonstration of this new scheme.