A Digital Bang-Bang Clock and Data Recovery Circuit Combined with ADC-Based Wireline Receiver

With the great increases in data transmission rate requirements, analog-to-digital converter (ADC)-based wireline receivers have received more and more attention due to their flexible and powerful equalization capabilities. Considering power consumption, baud-rate Mueller–Muller clock and data recovery (MM-CDR) circuits are widely used in ADC-based wireline receivers since MM-CDR circuits only need one sample signal per unit interval (UI). However, MM-CDR circuits need to set an additional Vref voltage to match the size of the main tap of the channel. If the Vref matching is not appropriate or the signal quality is good as a square wave, MM-CDR circuits cannot accurately lock on to a certain phase and instead drift within a phase range. Therefore, MM-CDR circuits are not as robust and stable as oversampled CDR circuits. In this study, a digital bang-bang clock and data recovery (DBB-CDR) circuit combined with an ADC-based wireline receiver was proposed. The DBB-CDR circuit could eliminate various unstable factors of MM-CDR circuits and achieve fast and robust phase locking without excessively increasing power consumption. A model of the DBB-CDR circuit was combined with an actual 32 Gb/s ADC-based wireline receiver, which was implemented in 28 nm CMOS technology to analyze the performance of the DBB-CDR circuit. The simulation results showed that the DBB-CDR circuit could achieve 0.42 UIpp JTOL@10MHz, and that the minimum JTOL value was 0.362 UIpp under a 0.04 UI variance of Gaussian jitter. The area and power consumption of the DBB-CDR circuit were only 64 μm2 and 0.02 mW, respectively; and the DBB-CDR circuit could also obtain very stable phase locking and demonstrated a fast frequency offset tracking ability when there was a frequency offset.