A Wideband Low-Power Current-Reuse RF-to-BB Receiver Using a Clock Strategy Technique

A wideband and low-power RF-to-baseband (BB) current-reuse receiver (CRR) front-end that employs a clock strategy is proposed to support software-defined radios (SDRs). It includes a capacitively cross-coupled common-gate low noise transconductance amplifier (LNTA) to amplify and convert the RF voltage to a current, a passive mixer to down-convert the RF current at 4 × the local-oscillator (LO) frequency to the intermediate frequency (IF) current using a clock strategy, an active-inductor (AI) technique to improve the noise-figure (NF) performance, and a transimpedance amplifier (TIA) to convert the IF current to a voltage at the output. To achieve low power consumption the receiver features: current-reuse between the LNTA and the BB circuits; current-mode harmonic recombination at the output of the passive mixer; and a clock strategy to reduce the dynamic power consumption of the clock generation for the dividers and the LO buffers. The proposed receiver is implemented in 22-nm CMOS technology and occupies an active area of 0.13mm ² . In the nominal condition, at an IF of 10MHz and an RF of 2.4GHz, it achieves a voltage gain of 36dB, a double-sideband (DSB) noise figure (NF) of 5.2dB, S 11 of less than −10dB and an IIP3 of −18.5dBm while consuming 2.44mA from a 1.2V supply voltage.