CNN Specific ISA Extensions Based on RISC-V Processors

The CNNs have achieved excellent performance in pattern recognition and target detection, which have a wide range of applications in industrial control, medical imaging, autonomous driving, and other fields. However, it is very inefficient to execute data-intensive CNN applications on edge devices with limited computing and power resources. It is necessary to add a domain-specific acceleration module on the edge devices to improve the performance when performing intensive calculations. In this work, we present ISA extensions based on the RISC-V ISA, including data operation instruction and data transfer instruction, aimed at boosting the computational efficiency of CNNs on edge devices. The microarchitecture supporting our proposed extensions is built on top of an open-source RISC-V core. In addition, extended instructions have been added to the GCC Binutils toolchain. To evaluate the effect of our extended instructions, we performed a set of workloads on the baseline and extended core, our proposed ISA extensions have a speed-up ratio of 1.5$\times$ when executing a CNN, and reaches 2.48$\times-2.82\times$ when only performing convolution calculations. The results show that our proposed ISA extensions can effectively improve the performance of CNNs.