System Development of Calibration-Free 20.7-Bit Chipless RFID Without Iterative Optimization of Tag Configurations

Earlier studies have improved the data capacity of frequency-coded chipless radiofrequency identification (RFID) to 100 bits, but these high-density tags may suffer from two limitations, including the design complexity for billions of tags and an additional procedure for measuring clutter. In this paper, a calibration-free chipless RFID system with 20.7-bit capacity is proposed; moreover, the design of the 1.68 million tags is highly efficient, preventing individual and iterative optimization for such large numbers of configurations. These distinct features are obtained by integrating the signal processing of reader and the resonance synthesis of tags. The signal processing employs short-time Fourier transform (STFT) and enhanced filtering to achieve calibration-free detection. The resonance synthesis features minimized numbers of geometric parameters, reduced mutual coupling between resonators, and response surface models for the resonant frequency to realize noniterative optimization. The proposed system is validated by three approaches. First, residual plots indicate that the range of residuals is confined to the average bandwidth of frequency slots. Second, 36 IDs are sampled and automatically transformed into chipless tags. The measured reliability of four bands is as high as 100%, 95.0%, 98.3%, and 93.9%, respectively. Finally, the parameterization of signal processing is validated by time-frequency analysis and reliability.