Design Methodology for Scalable 2.5D/3D Heterogenous Tiled Chiplet Systems

The incentives for chiplet based systems have been multifold with current workloads, heterogeneous integration, and rising cost of technology downscaling. This process is commonly known as die disaggregation where multiple functional chiplets are integrated on an interposer to form a bigger complex system. Current application trends demand these tiled systems to support co-existing chiplets with different technology nodes and different inter-die-interconnect requirements. In this paper, we describe the methodology aspects of co-designing functional chiplets, interposer and package level interconnects. We describe the advantages of chiplet reusability and establishing high throughput inter die connectivity.